Modern integrated circuits are required to perform multiple tasks at high speed. Each task, as well as multiple tasks, can be implemented by executing many instruction groups (also referred to as kernels). Usually, an instruction cache cannot store all the instruction groups, but rather only one or few instruction groups. Thus, once a new instruction group is required by the processor it should be fetched to the instruction cache.
In order to reduce the time (and performance) penalty resulting from fetching a new instruction group from a high level memory unit, unique pre-fetch instructions, to be executed by the processor, were developed. Various systems and method that use unique instructions are illustrated in European patent EP1096371B1 titled “A method and apparatus for prefetching instructions”, and in PCT patent application serial number PCT/US96/19469 titled “Cache multi-block touch mechanism for object oriented computer system”, both being incorporated herein by reference.
The execution of these dedicated instructions required to re-design the processor. Such re-design can be too costly, especially when the designers wish to re-use a processor that is not adapted to execute these unique instructions.
There is a need to provide efficient devices and methods for fetching instructions.